VHDL Vector passing -

i want pass value 1 vector another. can way?

vector_one : out std_logic_vector (3 downto 0); vector_two : out std_logic_vector (3 downto 0);  vector_one <= vector_two; 

the vector_one output port (mode out), , reading allowed in vhdl-2008, can do:

vector_one <= vector_two; 

however, in vhdl-2002 not allowed read output port, must drive both outputz source, vector_source, like:

vector_one <= vector_source; vector_two <= vector_source; 

generally, should avoided duplicate output signal that, since not obvious use of module output driven identical values, makes harder understand module use.