embedded c - real time clock - conter control register -


in rtc_callback() below, happening on line rtc[qm_rtc_0].rtc_ccr |= rtc_ccr_interrupt_enable;?

i've included register map below also.

in rtc counter control register , why "or in" interrupt enable? or happening?

define bit(x) (1u << (x)) #define rtc_ccr_interrupt_enable bit(0)  //==========================================================================  void rtc_callback(void *data) {    // bump time count onwards   rtc_set_alarm(qm_rtc_0, (rtc[qm_rtc_0].rtc_ccvr + alarm));    rtc[qm_rtc_0].rtc_ccr |= rtc_ccr_interrupt_enable; }   //==========================================================================   int rtc_init(void (*cb)(void *)) {    rtc_config_t cfg;    cfg.init_val = 0;   cfg.alarm_en = true;   cfg.alarm_val = alarm;    cfg.callback = rtc_callback;   cfg.callback_data = null;   global_rtc_cb = cb;    irq_request(irq_rtc_0, rtc_isr_0);   clk_periph_enable(clk_periph_rtc_register | clk_periph_clk);   rtc_set_config(rtc_0, &cfg);    return 0; }  /** rtc register map. */ typedef struct {     rw uint32_t rtc_ccvr;    /**< current counter value register */     rw uint32_t rtc_cmr;         /**< current match register */     rw uint32_t rtc_clr;         /**< counter load register */     rw uint32_t rtc_ccr;         /**< counter control register */     rw uint32_t rtc_stat;    /**< interrupt status register */     rw uint32_t rtc_rstat;  /**< interrupt raw status register */     rw uint32_t rtc_eoi;         /**< end of interrupt register */     rw uint32_t rtc_comp_version; /**< end of interrupt register */ } rtc_reg_t;


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