When do you use a block statement in a VHDL design and when do you not? -


i come sw world , i've started create fpga designs in vhdl. i've read block concurrent statement , principal uses organize architecture grouping concurrent code , guard signals, not recommendable.

but 1 of many possibilities in order implement same functionality. instance, i've been implemented crc frame checker vhdl function. has 1 bit value input, , return register cumulative crc value of bit inputs.

i think same functionality can implemented block. best option resource utilization? when use block , when not? best case implement block?

thanks,


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