fsm - coffee vending machine simulation in verilog with test bench issue -

i have written verilog code simple coffee vending machine inputs

25ps,50ps,75ps , 1

as

"00","01","10" , "11"

respectively. coffee cost 1 rs. if more 1rs inserted, balance returned. balance

01, 10, 11

as

25ps, 50ps, 1rs

respectively. simulate without test bench. simulation takes double clock pulse output.(when put 25 ps 8 times or 8 clock pulses required getting output. expected clock pulse 4). why happens? , didn't output when using test bench. please me correct test bench , programme. clock frequency divider necessary while doing programme in fpga board see output? working expected when programmed fpga board.im using xilinx vivado 2015.2 tool , zynq board.please me solve these issues

//programme module main( input clk, input rst, input [1:0] money, output coffee, output [1:0] balance );      reg coff; reg  [1:0] bal; reg  [2:0] pr_st; reg  [2:0] nx_st; parameter [2:0] a=3'b000; parameter [2:0] b=3'b001; parameter [2:0] c=3'b010; parameter [2:0] d=3'b011; parameter [2:0] e=3'b100; parameter [2:0] f=3'b101; parameter [2:0] g=3'b110; parameter [2:0] h=3'b111;  @ (posedge clk or posedge rst) begin if(rst) pr_st <= a; else  pr_st <= nx_st; end  @(posedge clk)          begin case(pr_st) : if(money == 2'b00) // input money 25ps begin nx_st <= b;  end else if(money == 2'b01)  // input money 50ps begin nx_st <= c;                        end else if(money == 2'b10)  // input money 75ps begin nx_st <= d;                         end else if(money == 2'b11) begin nx_st <= e;                    end b : if(money == 2'b00)     begin nx_st <= c;                          end  else if(money == 2'b01)  begin nx_st <= d;  end else if(money == 2'b10) begin nx_st <= e;                        end   else if(money == 2'b11) begin  nx_st <= f;                         end   c : if(money == 2'b00)          begin nx_st <= d;                       end  else if(money == 2'b01) begin  nx_st <= e;                         end  else if(money == 2'b10) begin  nx_st <= f;                       end else if(money == 2'b11) begin   nx_st <= g;                       end        d : if(money == 2'b00) begin            nx_st <= e;                           end else if(money == 2'b01)   begin nx_st <= f;                         end else if(money == 2'b10)   begin nx_st <= g;  end else if(money == 2'b11) begin nx_st <= h;                       end e :   nx_st <= a; f :   nx_st <= a; g :   nx_st <= a; h :   nx_st <= a; default : nx_st <= a;            endcase end  //output logic @( posedge clk or pr_st) begin case(pr_st) a: begin coff <= 1'b0; bal <= 2'b00;  end  b: begin coff <= 1'b0; bal <= 2'b00;  end  c: begin coff <= 1'b0; bal <= 2'b00;  end  d: begin coff <= 1'b0;  bal <= 2'b00;  end  e: begin coff <= 1'b1; bal<= 2'b00;         end f: begin coff <= 1'b1; bal <= 2'b01;        end g: begin coff <= 1'b1; bal <= 2'b10; end h: begin  coff <= 1'b1; bal <= 2'b11;        end default : begin off <=1'b0; bal <= 2'b00; end   endcase                        end   assign coffee = coff; assign balance = bal;  endmodule  //test bench module tb_main( ); reg clk; reg rst; reg [1:0] money; wire coffee; wire [1:0] balance;  main dut( clk, rst, money, coffee, balance); begin #200 clock = ~clk;  end   initial begin rst = 1'b1; #100 rst = 1'b0; money = 2'b00; // putting 25ps 4 times coffee #400 money = 2'b01; //putting 50ps 2 times coffee #200 money = 2'b10;// putting 75ps 2 times coffee #200 money = 2'b11;// putting 1 rs single time g #100 money = 2'b01; // putting 1st 25ps ,  50ps n second clock cycle #100 money = 2'b10; #200 $finish end  endmodule 

you need initialize clock signal known value in testbench. should speed clock because money input changes faster clock:

initial clk = 0; begin     #10 clk = ~clk;  end