scala - Chisel3. Functional Module Mux4 -

i'm learning chisel following documentation on github

thus far, worked flawlessly. i'm stuck @ chapter 13, "functional module creation"

i can't code work. created .scala classes in copy of chisel-template-project. here wrote / copied create mux4 variable bit width:

/chisel-template/src/main/scala/mux4.scala

import chisel._  class mux4(w: int) extends module {   val io = io(new bundle {         val sel = uint(input, 2)         val in0 = uint(input, w)         val in1 = uint(input, w)         val in2 = uint(input, w)         val in3 = uint(input, w)         val out = uint(output, w)   })    io.out := mux2(io.sel(1),                      mux2(io.sel(0), io.in0, io.in1),                     mux2(io.sel(0), io.in2, io.in3)) }   class mux2(w: int) extends module {   val io = io(new bundle {         val sel = bool(input)         val in0 = uint(input, w)         val in1 = uint(input, w)         val out = uint(output, w)   })    when(io.sel) {     io.out := io.in0   }.otherwise {     io.out := io.in1   } }   object mux2 {   def apply(sel: uint, in0: uint, in1: uint): uint = {     val m = new mux2(in0.getwidth)      m.io.sel := sel.tobool()     m.io.in0 := in0     m.io.in1 := in1     m.io.out   } } 

the tester scala class wrote:

/chisel-template/src/test/scala/mux4test.scala

import chisel.iotesters.{chiselflatspec, driver, peekpoketester}  class mux4test(c: mux4) extends peekpoketester(c) {        val sel = 3       val (in0, in1, in2, in3) = (5, 7, 11, 15)        poke(c.io.sel, sel)       poke(c.io.in0, in0)       poke(c.io.in1, in1)       poke(c.io.in2, in2)       poke(c.io.in3, in3)       step(1)       system.out.println("circuit: "+peek(c.io.out)           +"  expected: "+testmux4.result(sel, in0, in1, in2, in3)) }  object testmux4{   def result(sel: int, in0: int, in1: int, in2: int, in3: int): int = {     val out = sel match{       case 0 => in3       case 1 => in2       case 2 => in1       case 3 => in0     }     out   } }  class mux4tester extends chiselflatspec {   behavior of "mux4"   backends foreach {backend =>     should s"do mux4 $backend" in {       driver(() => new mux4(4), backend)(c => new mux4test(c)) should (true)     }   } } 

the important part output

step 0 -> 1 circuit: 0  expected: 5 

the mux4 class (circuit) returns 0 output, whereas should 5, because selection process follows:

00 -> io.out = in3 = 15

01 -> io.out = in2 = 11

10 -> io.out = in1 = 7

11 -> io.out = in0 = 5

in mux4test.scala class wrote val sel = 3. bit representation of 11 , therefore i'd expect in0 = 5.

where wrong?

thank interest in chisel!

i ran example, , after scratching head while found problem: when instantiate chisel module, need make sure wrap in module(...) (edit: code on wiki omitted wrapper. has been fixed). thus, object mux2 should instead be:

object mux2 {   def apply(sel: uint, in0: uint, in1: uint): uint = {     val m = module(new mux2(in0.getwidth)) // <- see here     m.io.sel := sel.tobool()     m.io.in0 := in0     m.io.in1 := in1     m.io.out   } } 

with change, looks code works!