hdl - system verilog disabling `ifndef blocks in specific instances -

in system verilog design, have top-module, sub-module , sub-sub module. sub-sub module instantiated in sub-module instantiated in top module.top module has instance of sub-sub module.the hierarchy tree shown below

the sub-sub module definition has code written in 'ifndef block this

module sub_sub() { ........... `ifndef off <code avoid> `endif ........... } 

how can disable code avoid in sub-sub module instance1 during compilation? used `define off in sub-module instance disables code avoid instances.

the cleaner solution pass parameter , use generate-if/case statement. example:

module sub_sub #(parameter off=0) ( ... );   generate     if (off) begin       <code avoid>     end   endgenerate endmodule  module sub ( ... );   ...   sub_sub #( .off(1'b1) ) inst ( ... ); endmodule  module top ( ... );   ...   sub inst0 ( ... );   sub_sub #( .off(1'b0) ) inst1 ( ... ); endmodule 

technically the if (off) not need in explicit generate-endgenerate; inferred otherwise. recommended human readability.

for full detail on generate blocks, refer ieee std 1800-2012 § 27. generate constructs