add - Best and Fastest Way for adding two std_logic_vector in VHDL -

in vhdl if have std_logic_vector per following declaration:

signal ram_addr : std_logic_vector (2 downto 0) := (others => '0'); 

if try increment address in loop '+' operator per following:

for in 0 7 loop    ram_rw <= '1';    wait until key_num'event;                        ram_rw <= '0';    ram_addr <= ram_addr + "1"; end loop; 

i face following error:

error (10327): vhdl error @ x.vhd(40): can't determine definition of operator ""+"" -- found 0 possible definitions

can suggest best , fastes way solve (maybe without using different type of data integer)?

up using following (bad) solution:

case ram_addr   when "000" =>     ram_addr <= "001";   when "001" =>     ram_addr <= "010";   when "010" =>     ram_addr <= "011";   when "011" =>     ram_addr <= "100";   when "100" =>     ram_addr <= "101";   when "101" =>     ram_addr <= "110";   when "110" =>     ram_addr <= "111";   when "111" =>     ram_addr <= "000";   when others =>     ram_addr <= "000"; end case; 

thanks in advance,

the recommended way use numeric_std package, , instantiate signal of type unsigned.

use ieee.numeric_std.all; 

...

signal ram_addr : unsigned (2 downto 0) := (others => '0'); 

...

ram_addr <= ram_addr + 1; 

you can try other methods involve fighting type system, if used using appropriate types on, can save kinds of bug in future. in opinion, using appropriate types can lead more readable code.